It takes 10 milliseconds to search the TLB and 80 milliseconds to access the physical memory. 27 Consider a cache (M1) and memory (M2) hierarchy with the following characteristics:M1 : 16 K words, 50 ns access time M2 : 1 M words, 400 ns access time Assume 8 words cache blocks and a set size of 256 words with set associative mapping. Effective memory Access Time (EMAT) for single level paging with TLB hit ratio: Here hit ratio =80% means we are taking0.8,memory access time (m) =100ns,Effective memory Access Time (EMAT) =140ns and letTLB access time =t. A single-level paging system uses a Translation Look-aside Buffer (TLB). 1 Memory access time = 900 microsec. To make sure it has clean pages there is a background process that goes over dirty pages and writes them out. I was solving exercise from William Stallings book on Cache memory chapter. 2. Which of the following is not an input device in a computer? 130 ns = Hx{ 20 ns + 100 ns } + (1-H) x { 20 ns + (1+1) x 100 ns }, 130 ns = H x { 120 ns } + (1-H) x { 220 ns }. How to tell which packages are held back due to phased updates. Is it possible to create a concave light? a) RAM and ROM are volatile memories Assume a two-level cache and a main memory system with the following specs: t1 means the time to access the L1 while t2 and t3 mean the penalty to access L2 and main memory, respectively. Windows)). So, every time a cpu generates a virtual address, the operating system page table has to be looked up to find the corresponding physical address. Not the answer you're looking for? = 0.8 x{ 20 ns + 100 ns } + 0.2 x { 20 ns + (3+1) x 100 ns }. He tried to combine 20ns access time for the TLB with 80ns time for memory to make a nice 100ns time. Note: We can use any formula answer will be same. The average memory access time is the average of the time it takes to access a request from the cache and the time it takes to access a request from main . Here it is multi-level paging where 3-level paging means 3-page table is used. has 4 slots and memory has 90 blocks of 16 addresses each (Use as If the TLB hit ratio is 80%, the effective memory access time is. It takes 20 ns to search the TLB and 100 ns to access the physical memory. The problem was: For a system with two levels of cache, define T c1 = first-level cache access time; T c2 = second-level cache access time; T m = memory access time; H 1 = first-level cache hit ratio; H 2 = combined first/second level cache hit ratio. You could say that there is nothing new in this answer besides what is given in the question. Daisy wheel printer is what type a printer? Are those two formulas correct/accurate/make sense? Actually, this is a question of what type of memory organisation is used. Why are physically impossible and logically impossible concepts considered separate in terms of probability? If we fail to find the page number in the TLB, then we must first access memory for. But it is indeed the responsibility of the question itself to mention which organisation is used. The 'effective access time' is essentially the (weighted) average time it takes to get a value from memory. If it was a 3 level paging system, would TLB_hit_time be equal to: TLB_search_time + 3* memory_access_time and TLB_miss_time be TLB_search_time + 3*(memory_access_time + memory_access_time) and EAT would then be the same? Which of the following control signals has separate destinations? Main memory access time is 100 cycles to the rst bus width of data; after that, the memory system can deliv er consecutiv e bus widths of data on eac h follo wing cycle. When an application needs to access data, it first checks its cache memory to see if the data is already stored there. Average memory access time is a useful measure to evaluate the performance of a memory-hierarchy configuration. It tells us how much penalty the memory system imposes on each access (on average). Calculation of the average memory access time based on the following data? You are not explicit about it, but I would assume the later if the formula didn't include that 0.2*0.9, which suggests the former. It is given that effective memory access time without page fault = i sec, = (1 / k) x { i sec + j sec } + ( 1 1 / k) x { i sec }. Before you go through this article, make sure that you have gone through the previous article on Page Fault in OS. The logic behind that is to access L1, first. It takes some computing resources, so it should actually count toward memory access a bit, but much less since the page faults don't need to wait for the writes to finish. Consider an OS using one level of paging with TLB registers. A write of the procedure is used. Ratio and effective access time of instruction processing. The nature of simulating nature: A Q&A with IBM Quantum researcher Dr. Jamie We've added a "Necessary cookies only" option to the cookie consent popup. Connect and share knowledge within a single location that is structured and easy to search. Why are non-Western countries siding with China in the UN? TLB hit ratio is nothing but the ratio of TLB hits/Total no of queries into TLB. Effective access time = (h x c) + ( (1-h) x ( c + m )) = (0.95 x 5) + ( (0.05) x (5 + 40)) nanoseconds = 4.75 + 2.25 nanoseconds = 7 nanoseconds Next Previous Related Questions Q: Assume that a given system's main memory has an access time of 6.0 ns, and its cache has an access.. Answer: To calculate: Hit ratio for effective access time of 1.5 ns. It takes 20 ns to search the TLB and 100 ns to access the physical memory. Can I tell police to wait and call a lawyer when served with a search warrant? Connect and share knowledge within a single location that is structured and easy to search. Example 3:Here calculating the hit ratio, where EMAT, TLB access time, and memory access time is given. Virtual Memory If the effective memory access time (EMAT) is 106ns, then find the TLB hit ratio. Calculation of the average memory access time based on the following data? So, the percentage of time to fail to find the page number in theTLB is called miss ratio. Paging in OS | Practice Problems | Set-03. This is the kind of case where all you need to do is to find and follow the definitions. As both page table and page are in physical memory T (eff) = hit ratio * (TLB access time + Main memory access time) + (1 - hit ratio) * (TLB access time + 2 * main memory time) = 0.6* (10+80) + (1-0.6)* (10+2*80) LKML Archive on lore.kernel.org help / color / mirror / Atom feed help / color / mirror / Atom feed * Before this read chapter please follow the previous chapter first: Calculate Effective Access Time (EMAT). The cycle time of the processor is adjusted to match the cache hit latency. Because it depends on the implementation and there are simultenous cache look up and hierarchical. Site design / logo 2023 Stack Exchange Inc; user contributions licensed under CC BY-SA. Formula to calculate the Effective Access Time: Effective Access Time =Cache Hit RatioCache Access. Then the above equation becomes. As both page table and page are in physical memoryT(eff) = hit ratio * (TLB access time + Main memory access time) +(1 hit ratio) * (TLB access time + 2 * main memory time)= 0.6*(10+80) + (1-0.6)*(10+2*80)= 0.6 * (90) + 0.4 * (170)= 122, This solution is contributed Nitika BansalQuiz of this Question. What is the effective access time (in ns) if the TLB hit ratio is 70%? The candidates must meet the USPC IES Eligibility Criteria to attend the recruitment. By using our site, you (A) 120(B) 122(C) 124(D) 118Answer: (B)Explanation: TLB stands for Translation Lookaside Buffer. | solutionspile.com Does Counterspell prevent from any further spells being cast on a given turn? caching memory-management tlb Share Improve this question Follow EMAT for Multi-level paging with TLB hit and miss ratio: b) Convert from infix to reverse polish notation: (AB)A(B D . To find the effective memory-access time, we weight Effective memory Access Time (EMAT) for single-level paging with TLB hit ratio: Here hit ratio (h) =80% means here taking0.8, memory access time (m) =80ns and TLB access time (t) =10ns. much required in question). The time taken to service the page fault is called as, One page fault occurs every k instruction, Average instruction takes 100 ns of CPU time and 2 memory accesses, Time taken to replace dirty page = 300 time units. Use MathJax to format equations. if page-faults are 10% of all accesses. level of paging is not mentioned, we can assume that it is single-level paging. Can Martian Regolith be Easily Melted with Microwaves. If that is the case, a miss will take 20ns+80ns+80ns=180ns, not 200ns. It is a question about how we interpret the given conditions in the original problems. The UPSC IES previous year papers can downloaded here. (That means that the L1 miss p enalt y, assuming a hit in the L2 cac he, is 10 cycles.) EMAT for Multi-level paging with TLB hit and miss ratio: Same way we can write EMAT formula for multi-level paging in another way: Let, miss ratio =h, hit ration =(1 - h), memory access time =m, TLB access time = tand page-level = k. Effective memory Access Time (EMAT) for single level paging with TLB hit and miss ratio: EMAT for Multi level paging with TLB hit and miss ratio: To get updated news and information subscribe: 2023 MyCareerwise - All rights reserved, The percentage of times that the required page number is found in the. So, here we access memory two times. Which has the lower average memory access time? The issue here is that the author tried to simplify things in the 9th edition and made a mistake. first access memory for the page table and frame number (100 Cache Access Time Example Note: Numbers are local hit rates - the ratio of access that go to that cache that hit (remember, higher levels filter accesses to lower levels) . Can I tell police to wait and call a lawyer when served with a search warrant? The expression is actually wrong. Do roots of these polynomials approach the negative of the Euler-Mascheroni constant? The formula for calculating a cache hit ratio is as follows: For example, if a CDN has 39 cache hits and 2 cache misses over a given timeframe, then the cache hit ratio is equal to 39 divided by 41, or 0.951. It is given that effective memory access time without page fault = 20 ns. It first looks into TLB. That gives us 80% times access to TLB register plus access to the page itself: remaining 20% of time it is not in TLB cache. The Union Public Service Commission released the UPSC IES Result for Prelims on 3rd March 2023. How to calculate average memory access time.. Your answer was complete and excellent. By clicking Accept all cookies, you agree Stack Exchange can store cookies on your device and disclose information in accordance with our Cookie Policy. Watch video lectures by visiting our YouTube channel LearnVidFun. It should be either, T = 0.8(TLB + MEM) + 0.2((0.9(TLB + MEM + MEM)) + 0.1(TLB + MEM + 0.5(Disk) + 0.5(2Disk + MEM))), T = 0.8(TLB + MEM) + 0.1(TLB + MEM + MEM) + 0.1(TLB + MEM + 0.5(Disk) + 0.5(2Disk + MEM)). Products Ansible.com Learn about and try our IT automation product. d) A random-access memory (RAM) is a read write memory. Outstanding non-consecutiv e memory requests can not o v erlap . Assume that load-through is used in this architecture and that the If a law is new but its interpretation is vague, can the courts directly ask the drafters the intent and official interpretation of their law? The address field has value of 400. we need to place a physical memory address on the memory bus to fetch the data from the memory circuitry. How is Jesus " " (Luke 1:32 NAS28) different from a prophet (, Luke 1:76 NAS28)? Miss penalty mean extra spent time beyond the time spent on checking and missing the faster caches. Note: The above formula of EMAT is forsingle-level pagingwith TLB. However, we could use those formulas to obtain a basic understanding of the situation. In this case the first formula you mentioned is applicable as access of L2 starts only after L1 misses. Assume that. In your example the memory_access_time is going to be 3* always, because you always have to go through 3 levels of pages, so EAT is independent of the paging system used. However, that is is reasonable when we say that L1 is accessed sometimes. Where TLB hit ratio is same single level paging because here no need access any page table, we get page number directly from TLB. Posted one year ago Q: If TLB hit ratio is 60% and effective memory access time is 160 ns, TLB access time is ______. Calculating effective address translation time. Then with the miss rate of L1, we access lower levels and that is repeated recursively. The result would be a hit ratio of 0.944. The static RAM is easier to use and has shorter read and write cycles. A TLB-access takes 20 ns as well as a TLB hit ratio of 80%. Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds and servicing a page fault takes 8 milliseconds. The actual average access time are affected by other factors [1]. An 80-percent hit ratio, for example, Stack Exchange network consists of 181 Q&A communities including Stack Overflow, the largest, most trusted online community for developers to learn, share their knowledge, and build their careers. b) Convert from infix to rev. Effective access time is increased due to page fault service time. ____ number of lines are required to select __________ memory locations. I would like to know if, In other words, the first formula which is. There is nothing more you need to know semantically. Full Course of Computer Organization \u0026 Architecture: https://youtube.com/playlist?list=PLV8vIYTIdSnar4uzz-4TIlgyFJ2m18NE3In this video you can learn about Cache Hit Time, Hit Ratio and Average Memory Access Time in Computer Organization \u0026 Architecture(COA) Course. the case by its probability: effective access time = 0.80 100 + 0.20 A 3 level paging scheme uses a Translation Look-aside Buffer (TLB). The access time of cache memory is 100 ns and that of the main memory is 1 sec. In 8085 microprocessor CMA, RLC, RRC instructions are examples of which addressing mode? If we fail to find the page number in the TLB, then we must first access memory for the page table and get the frame number and then access the desired byte in the memory. Number of memory access with Demand Paging. In this context "effective" time means "expected" or "average" time. To learn more, see our tips on writing great answers. An average instruction takes 100 nanoseconds of CPU time and two memory accesses. If effective memory access time is 130 ns,TLB hit ratio is ______. Site design / logo 2023 Stack Exchange Inc; user contributions licensed under CC BY-SA. 2. The best way to calculate a cache hit ratio is to divide the total number of cache hits by the sum of the total number of cache hits, and the number of cache misses. Consider a single level paging scheme with a TLB. Experts are tested by Chegg as specialists in their subject area. If the TLB hit ratio is 0.6, the effective memory access time (in milliseconds) is _________. (ii)Calculate the Effective Memory Access time . For the sake of discussion again, if we assume that t2 and t3 mean the time to access L2 and main memory directly assuming there is no caches at all, respectively, then we should claim there is not enough information to compute a reasonable answer. By clicking Accept all cookies, you agree Stack Exchange can store cookies on your device and disclose information in accordance with our Cookie Policy. when CPU needs instruction or data, it searches L1 cache first . nanoseconds) and then access the desired byte in memory (100 disagree with @Paul R's answer. It is a typo in the 9th edition. When a CPU tries to find the value, it first searches for that value in the cache. Become a Red Hat partner and get support in building customer solutions. This impacts performance and availability. For example, if you have 51 cache hits and three misses over a period of time, then that would mean you would divide 51 by 54. - Inefficient memory usage and memory leaks put a high stress on the operating virtual memory subsystem. i =1 Because f i = (1 h1 ) (1 h2 ) . (1 hi 1 ) hi , the above formula can be rewritten as Teff = h1t1 + (1 h1 ) h2 t 2 + . + (1 h1 ) h2 t 2 (1 hn 1 ) Using Verilog, designed a 16-block direct-mapped, write-back cache with 2 words/line, that supports same cycle read/write hit. Calculating Effective Access Time- Substituting values in the above formula, we get- Effective Access Time = 0.8 x { 20 ns + 100 ns } + 0.2 x { 20 ns + (3+1) x 100 ns } = 0.8 x 120 ns + 0.2 + 420 ns = 96 ns + 84 ns = 180 ns Thus, effective memory access time = 180 ns. Or if we can assume it takes relatively ignorable time to find it is a miss in $L1$ and $L2$ (which may or may not true), then we might be able to apply the first formula above, twice. The CPU checks for the location in the main memory using the fast but small L1 cache. Why do many companies reject expired SSL certificates as bugs in bug bounties? I can't understand the answer to this question: Consider an OS using one level of paging with TLB registers. * It is the first mem memory that is accessed by cpu. The average access time of the system for both read and write requests is, TPis the access time for physical memory, = (0.8 200 + 0.2 1000) nsec = 360 nsec. Do new devs get fired if they can't solve a certain bug? An instruction is stored at location 300 with its address field at location 301. Which of the following have the fastest access time? 1. It is given that one page fault occurs for every 106 memory accesses. 90% (of those 20%) of times the page is still mapped, but the address fell out of the cache, so we have to do extra memory read from the page map. Which of the following loader is executed. The TLB is a high speed cache of the page table i.e. Where: P is Hit ratio. Consider a two level paging scheme with a TLB. TRAP is a ________ interrupt which has the _______ priority among all other interrupts. Effective memory Access Time (EMAT) for single-level paging with TLB hit ratio: Here hit ratio (h) = 80% means here taking 0.8, memory access time (m) = 80ns and TLB access time (t) = 10ns. Can I tell police to wait and call a lawyer when served with a search warrant? But in case ofTLB miss when the page number is not present at TLB, we have to access the page table and if it is a multi-level page table, we require to access multi-level page tables for the page number. Now, substituting values in the above formula, we get-, = 10-6 x { 20 ns + 10 ms } + ( 1 10-6 ) x { 20 ns }, Suppose the time to service a page fault is on the average 10 milliseconds, while a memory access takes 1 microsecond. A place where magic is studied and practiced? This is due to the fact that access of L1 and L2 start simultaneously. If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 6 array, where each chip is 8K 4 bits? The nature of simulating nature: A Q&A with IBM Quantum researcher Dr. Jamie We've added a "Necessary cookies only" option to the cookie consent popup. So if a hit happens 80% of the time and a miss happens 20% of the time then the effective time (i.e. Effective Access Time With Page Fault- It is given that effective memory access time without page fault = 20 ns. How can this new ban on drag possibly be considered constitutional? ncdu: What's going on with this second size column? Assume no page fault occurs. Problem-04: Consider a single level paging scheme with a TLB. 160 ns = 0.6 x{ T ns + 100 ns } + 0.4 x { T ns + (1+1) x 100 ns }, 160 ns = 0.6 x { T ns + 100 ns } + 0.4 x { T ns + 200 ns }, 160 ns = 0.6T ns + 60 ns + 0.4T ns + 80 ns, 0.6T ns + 0.4T ns = 160 ns 60 ns 80 ns. Can archive.org's Wayback Machine ignore some query terms? A page fault occurs when the referenced page is not found in the main memory. You can see another example here. Is it a bug? A notable exception is an interview question, where you are supposed to dig out various assumptions.). @qwerty yes, EAT would be the same. Let the page fault service time be 10 ms in a computer with average memory access time being 20 ns. Assume no page fault occurs. (i)Show the mapping between M2 and M1. The idea of cache memory is based on ______. Effective Access time when multi-level paging is used: In the case of the multi-level paging concept of TLB hit ratio and miss ratio are the same. If you make 100 requests to read values from memory, 80 of those requests will take 100 ns and 20 of them will take 200 (using the 9th Edition speeds), so the total time will be 12,000 ns, for an average time of 120 ns per access. The cache access time is 70 ns, and the the TLB is called the hit ratio. Thus it exist a percentage of occurrences we have to include at least: Thanks for contributing an answer to Stack Overflow! This is better understood by. Which of the following sets of words best describes the characteristics of a primary storage device, like RAM ? , for example, means that we find the desire page number in the TLB 80% percent of the time. Here it is multi-level paging where 3-level paging means, level of paging is not mentioned, we can assume that it is, and Effective memory Access Time (EMAT) =, Difference between system call and library call, Hybrid Kernel and Nano Kernel or Pico Kernel, Long Term, Short-term and Mid-term Scheduler, Shortest Remaining Time First (SRTF) (Preemptive SJF), Special Example of SRTF with CPU and I/O Time, Inter-process communication and Synchronization, Process Synchronization as a solution of Critical Section, Requirement of Synchronization mechanisms, Lock variable with priority Inversion Problem, Comparison: synchronization solutions with busy waiting, Producer and Consumer problem with Race Condition, Solving the Producer-Consumer Problem Using Semaphores, NET and GATE question: Counting Semaphore, Binary Semaphore question on NET and GATE, Producer-Consumer Problem Using Semaphores, Dining Philosopher Problem algorithm and example, Barrier synchronism algorithm and example, Precedence graph for concurrency programming, Advantages and disadvantages Dynamic Linking, Related Questions: SET, NET, GATE and ISRO, Solution of External Fragmentation: Compaction, Algorithms for finding appropriate Holes in Memory, Protection in Contiguous Memory Allocation, Concept of Non-contiguous memory allocation, Calculation of Logical Address Bit and number of Pages, Calculation of Physical Address Bit and number of Frames, Effective Access Time using Hit & Miss Ratio, GATE and NET question on calculation EMAT, GATE/NET question on EMAT with Page fault, GATE/NET question on EMAT with Page Fault, Concept: Optimal page replacement algorithm, GATE Question: FIFO page replacement algorithm. Effective memory access time without page fault, = 0.9 x { 0 + 150 ns } + 0.1 x { 0 + (2+1) x 150 ns }, = 10-4x { 180 ns + 8 msec } + (1 10-4) x 180 ns, Effective Average Instruction Execution Time, = 100 ns + 2 x Effective memory access time with page fault, A demand paging system takes 100 time units to service a page fault and 300 time units to replace a dirty page. Difference between system call and library call, Hybrid Kernel and Nano Kernel or Pico Kernel, Long Term, Short-term and Mid-term Scheduler, Shortest Remaining Time First (SRTF) (Preemptive SJF), Special Example of SRTF with CPU and I/O Time, Inter-process communication and Synchronization, Process Synchronization as a solution of Critical Section, Requirement of Synchronization mechanisms, Lock variable with priority Inversion Problem, Comparison: synchronization solutions with busy waiting, Producer and Consumer problem with Race Condition, Solving the Producer-Consumer Problem Using Semaphores, NET and GATE question: Counting Semaphore, Binary Semaphore question on NET and GATE, Producer-Consumer Problem Using Semaphores, Dining Philosopher Problem algorithm and example, Barrier synchronism algorithm and example, Precedence graph for concurrency programming, Advantages and disadvantages Dynamic Linking, Related Questions: SET, NET, GATE and ISRO, Solution of External Fragmentation: Compaction, Algorithms for finding appropriate Holes in Memory, Protection in Contiguous Memory Allocation, Concept of Non-contiguous memory allocation, Calculation of Logical Address Bit and number of Pages, Calculation of Physical Address Bit and number of Frames, Effective Access Time using Hit & Miss Ratio, GATE and NET question on calculation EMAT, GATE/NET question on EMAT with Page fault, GATE/NET question on EMAT with Page Fault, Concept: Optimal page replacement algorithm, GATE Question: FIFO page replacement algorithm. Ratio and effective access time of instruction processing. Connect and share knowledge within a single location that is structured and easy to search. - Memory-intensive applications that allocate a large amount of memory without much thought for freeing the memory at run time can cause excessive memory usage. If it takes 100 nanoseconds to access memory, then a So, t1 is always accounted. memory (1) 21 cache page- * It is the fastest cache memory among all three (L1, L2 & L3). The cases are: I think some extra memory accesses should be included in the last two (swap) cases as two accesses are needed to mark the previous page unavailable and the new page available in the page table. Get more notes and other study material of Operating System. A cache memory that has a hit rate of 0.8 has an access latency 10 ns and miss penalty 100 ns. Learn more about Stack Overflow the company, and our products. Assume that Question Using Direct Mapping Cache and Memory mapping, calculate Hit Ratio and effective access time of instruction processing. When a system is first turned ON or restarted? If Cache Substituting values in the above formula, we get-, = 0.8 x{ 20 ns + 100 ns } + 0.2 x { 20 ns + (1+1) x 100 ns }. Watch video lectures by visiting our YouTube channel LearnVidFun. If TLB hit ratio is 50% and effective memory access time is 170 ns, main memory access time is ______. is executed using a 64KB cache, resulting in a hit rate of 97%, a hit time of 3 ns and the same miss penalty that in the previous case. (I think I didn't get the memory management fully). For example,if we have 80% TLB hit ratio, for example, means that we find the desire page number in the TLB 80% percent of the time. With two caches, C cache = r 1 C h 1 + r 2 C h 2 + (1 r 1 r 2 ) Cm Replacement Policies Least Recently Used, Least Frequently Used Cache Maintenance Policies Write Through - As soon as value is . A single-level paging system uses a Translation Look-aside Buffer (TLB) where memory access takes 100ns and hit ratio of TLB 80%. NOTE: IF YOU HAVE ANY PROBLEM PLZ COMMENT BELOW..AND PLEASE APPRECIATE MY HARDWORK ITS REALL. Questions and answers to Computer architecture and operating systems assignment 3 question describe the of increasing each of the following cache parameters Which of the above statements are correct ? Does a barbarian benefit from the fast movement ability while wearing medium armor? Get more notes and other study material of Operating System. Technique used to minimize the average memory access time : Reducing hit time, miss penalty or miss rate. To calculate a hit ratio, divide the number of cache hits with the sum of the number of cache hits, and the number of cache misses. Memory Stall Clock-cycles = ( Memory Access/Program ) X Miss Rate X Miss Penalties Memory Stall Clock-cycles = (Instructions/Program ) X ( Misses/Instructions ) X Miss Penalties Measuring and Improving Cache Performance : 1. The fraction or percentage of accesses that result in a miss is called the miss rate. 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Making statements based on opinion; back them up with references or personal experience. the time. That is. This value is usually presented in the percentage of the requests or hits to the applicable cache. The following equation gives an approximation to the traffic to the lower level. Then the above equation becomes effective-access-time = cache-access-time + miss-rate * miss-penalty Solution: Memory cost is calculated by; Ctotal= C1S1+C2S2+C3S3 G 15000, then S3=39.8 The effective memory access time is calculated as For each page table, we have to access one main memory reference.